1. Field of Invention
The present invention relates to a semiconductor device provided with element isolation regions filled with element isolation insulating films, and a method of manufacturing the same.
2. Description of the Related Art
Recently, a semiconductor device, particularly a non-volatile semiconductor storage device is manufactured by employing a process in which a gate electrode is formed prior to forming an element isolation region of STI (Shallow Trench Isolation) configuration. As disclosed in JP-A-2002-110822, such process forms a gate insulating film on a semiconductor substrate whereupon a film (a floating gate, for example) is further formed that constitutes a gate electrode. Thereafter an element isolation trench filled with an element isolation insulation film is formed in a predetermined direction in the substrate surface. Thus, the gate insulating film and gate electrode are processed.
The method disclosed in JP-A-2002-110822 involves the following steps. A tunnel insulating film (corresponding to gate insulating film) is formed by thermal oxidation process over a silicon substrate (corresponding to a semiconductor substrate). Formed thereafter is a polycrystalline silicon layer (corresponding to a floating gate electrode film) doped with impurities. Then, a silicon nitride film serving as a stopper for CMP (Chemical Mechanical Polish) process is formed whereafter a silicon oxide film used as a mask in RIE process is formed by LPCVD (Low-Pressure Chemical Vapor Deposition). Subsequently, the silicon oxide film, silicon nitride film, polycrystalline silicon layer, and tunnel insulating film are etched sequentially. Then, the silicon substrate is etched to form the element isolation trench.
After several successions of steps, the element isolation trench is completely filled with silicon oxide film deposited by plasma CVD process and the silicon oxide film overlaying the silicon nitride film is planarized by CMP process. Finally, the silicon nitride film serving as a stopper film is removed. The floating gate electrode, the gate insulating film and the element isolation insulating film are formed by the above described process.
In employing the manufacturing method disclosed in JP-A-2002-110822, each film is deposited over the semiconductor substrate surface in a predetermined film thickness. Trenches oriented in a predetermined direction are formed on the substrate surface and the element isolation insulating film is filled therein. Then, an impurity-doped polycrystalline silicon layer having high electrical conductivity is removed in an intersecting direction that intersects the predetermined direction in the substrate surface. Subsequently, by isolating the adjoining floating gate electrodes, two-dimensional floating gate electrodes are formed over the semiconductor substrate surface.
Thus, floating gate electrodes of high spatial efficiency can be formed on the semiconductor substrate surface. This method isolates the floating gate electrode films in two dimensions namely in the predetermined direction and the intersecting direction by removing the floating gate electrode film formed over the semiconductor substrate surface. However, the upper surface of the element isolation insulating film needs to be formed higher than the gate insulating film upper surface. Therefore, the attempt to completely remove the floating gate electrode film formed between the element isolation insulating films fails, leaving remainder floating gate electrode film along the sidewall of the element isolation insulating film in the trench forming direction (predetermined direction). This leads to an electrical conductive connection between the neighboring floating gates in the predetermined direction, which requires defective influence on the device.
Nowadays, subject to the increasing need to scale-down the circuit design rules, the width of the floating gate electrode film interposed between the element isolation insulating films is becoming narrower. This leads to an increase in the trench aspect ratio, requiring critical etching conditions upon removing the floating gate electrode film formed in the gate electrode isolation region.